1. Field of the Invention
The present invention relates to a memory circuit for writing data into a memory device, and more particularly, to a memory circuit capable of preventing erroneous writing into a memory device.
2. Description of the Related Art
First, description is given of a comparison between a fuse and a memory element that are used for trimming of analog quantity.
Most of integrated circuits (ICs) controlling analog quantity are trimmed for adjusting the analog quantity. There are some kinds of trimming method therefor. Three representative ones are described below:
(1) laser fuse method: a method in which a fuse is blown through irradiation of a laser;
(2) electrical fuse method: a method in which a fuse is blown through application of a large amount of current; and
(3) memory method: a method in which information is stored in a memory element, such as an erasable programmable read-only memory (EPROM).
In a broad sense, a fuse may be regarded as a kind of one-time programmable memory. However, the fuse is not called “memory” in general, and hence is not treated as a memory in this specification. As the EPROM, there is widely used a transistor whose threshold voltage Vth varies when carriers are injected into its floating gate by means of Fowler-Nordheim (FN) tunnel current or hot carriers.
Various ways of trimming can be found, and to facilitate understanding thereof, description is given with reference to FIG. 2. FIG. 2 illustrates a circuit called voltage detector, in which an output is inverted depending on whether a power supply voltage is higher or lower than a given value. The voltage detector is widely used for the purpose of power supply voltage monitoring.
An outline of operations of the voltage detector is described. Resistive elements 7 are disposed between a power supply VDD and a ground VSS so that a potential of the power supply VDD is divided with reference to the ground VSS. A comparator compares a potential determined by the potential dividing with a reference potential, and an output level of the comparator is inverted depending on whether the potential is higher or lower than the reference potential. The output level is shaped by an amplifier to be output.
A potential value at which the output level is inverted may be changed by division ratios of resistances. Among actual products, a value of the reference potential varies due to manufacturing fluctuations. The variations may cancel out one another by adjustments to the division ratios of the resistances. Thus, when the division ratio is enabled to be adjusted to an arbitrary value, the voltage detector capable of inverting its output at a desired voltage may be obtained.
The adjustment to the division ratio is realized by the following configuration. That is, fuses 8 and the resistive elements 7 are arranged in parallel with each other, and a resistive element 7 whose corresponding fuse 8 is blown functions as a resistor, whereas a resistive element 7 whose corresponding fuse 8 is not blown does not function as a resistor because this resistive element is short-circuited by the fuse. In general, this adjustment is called trimming. The voltage detector is merely employed as an example to describe the trimming because the voltage detector allows the simplest description of the trimming. Accordingly, the trimming is not limitedly performed in the circuit described above.
The laser fuse method is a method in which a target fuse is irradiated with a laser so that the fuse is blown, to thereby perform desired trimming. This method has an advantage that there is no need to provide a circuit for selecting which of the fuses is to be cut, and an external terminal. The trimming is performed before a chip is assembled into a package because the fuse cannot be irradiated with the laser in a packaged state.
A problem of this method is that trimming may not be performed in a packaged state. Analog quantity varies during a packaging process and during a reflow process of mounting the chip onto a board. For this reason, the trimming is desired to be performed after the reflow process, whereas the trimming may not be performed in actuality because the laser irradiation cannot be performed in the packaged state. Accordingly, in many cases, taking the variations into consideration, such a specification range of characteristics is adopted that is narrower than a specification range of finally-required characteristics. As a result, there arise problems of reduced yields, an increased chip area due to an additional circuit for achieving high precision, and the like. Besides, the laser fuse method has another problem that the method cannot be applied to a product necessary to be trimmed by a product purchaser on its own.
Next, the electrical fuse method is described. The electrical fuse method is a method in which a large amount of current is caused to flow through a target fuse so that the target fuse generates heat and is blown by the heat, to thereby perform desired trimming. This method enables the trimming to be performed in a packaged state because the trimming is an electrical trimming, and hence the above-mentioned problems may be avoided.
In this method, a large amount of current necessary for electrically blowing a fuse needs to be caused to flow through the fuse, and hence an external terminal is provided for each fuse in many cases. The external terminal is called pad, and the pad generally has a dimension of approximately 100 μm by 100 μm. Thus, compared to the laser fuse method, a significantly large area is required.
In addition, in order to perform trimming in a packaged state, each of the pads needs to be connected to a pin of a package, with the result that the number of pins of the package is significantly increased. JP 06-37254 A discloses a way of solving the problem of the increased number of pads. According to the method disclosed in JP 06-37254 A, the required number of pads may be reduced to two, which produces an effect of significantly reducing the area.
However, the method disclosed in JP 06-37254 A requires a serial-to-parallel converter for converting serial data into parallel data, two pads for inputting information to the serial-to-parallel converter, and a transistor that is capable of causing a large amount of current to flow. Thus, there remains a problem that the area is still large compared to the laser fuse method.
Next, the memory method is described. The memory method is a method employing a memory element instead of a fuse, and trimming is generally performed with the following configuration. That is, as illustrated in FIG. 3, transistors 10 are disposed in parallel with the resistive elements 7, and respective gate potentials of the transistors 10 are controlled by memory cells 9. When a transistor 10 is turned OFF, a corresponding resistive element 7 functions as a resistor, whereas when a transistor 10 is turned ON, a corresponding resistive element 7 is short-circuited by the turned-ON transistor 10.
Such a non-volatile memory element as the EPROM continues to retain stored information even after its power supply has been cut off, and hence the non-volatile memory element is suitable for use in trimming.
Each of the memory cells 9 has such a configuration as illustrated in FIG. 4. The memory cell 9 includes a memory element 12 formed of an N-channel transistor having a floating gate structure. In general, writing is performed by injecting electrons into a floating gate of the N-channel transistor. When the electrons have been injected into the floating gate, a channel of the N-channel transistor is less likely to be formed, resulting in an increased threshold Vth. FIG. 5 illustrates a relation between a control gate voltage VCG and a drain current of the memory element 12. As illustrated in FIG. 5, information is stored by utilizing the fact that the threshold Vth is increased after the writing.
The trimming is performed by the writing into the memory element, and hence there require a circuit for selecting the memory element and an external terminal.
The memory method also has an advantage that the trimming may be performed after the packaging process. However, the memory method requires a serial-to-parallel converter for selecting a memory element to be trimmed, and pads for inputting a signal for the selection to the serial-to-parallel converter, similarly to the case of the electrical fuse method disclosed in JP 06-37254 A. The memory method is different from the electrical fuse method in that a large amount of current is not required and an area may be thus reduced correspondingly to a transistor for causing a large amount of current to flow. However, this merely means that the area may be reduced compared to the electrical fuse method, and hence the memory method still has a problem of an increased area compared to the laser fuse method. Besides, the memory method has another problem that each memory element needs to be provided with an erroneous write prevention function in practical use and a circuit therefor thus needs to be provided.
JP 2003-110029 A discloses a technology for attempting to solve the above-mentioned problems. As compared to the laser fuse method, the technology, however, requires at least two pads and a circuit that is unnecessary in the laser fuse method, leading to an inevitable increase in a chip area.
As described above, in order to enable trimming to be performed in a packaged state, the conventional technology requires extra pads and an extra circuit (hereinafter respectively referred to as additional pads and additional circuit), as compared to the case of the laser fuse method. As a result, there arises a problem of an increased chip size.